The present invention relates to the field of semiconductor technology, and particularly relates to a method of forming a semiconductor device.
In the field of semiconductor technology, fin-type field effect transistors (FinFET) have been widely used due to their advantages. Fin-type field effect transistors not only have suppressed short-channel effects (SCE), but also have many other advantages. For example, they may be formed by using a self-aligned double patterning (SADP) technology.
However, in the conventional processes of forming a fin-type field effect transistor, during the process of etching the dielectric layer (the isolation material layer) located near the fin-type structure to form the recesses, because of etching selectivity ratio problems, the shallow trench isolation in the fin cut area (the area near the fin-type structure where the etching is performed) is often subject to excessive etching. This phenomenon will affect device performance and reliability.